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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. ad9948 10-bit ccd signal processor with precision timing core functional block diagram clamp dout ccdin reft refb internal registers 6db to 42db sync generator sdata sck sl hblk 10 vga ad9948 precision timing core 10-bit adc v ref internal clocks pxga cds horizontal drivers 4 rg h1?4 hd vd cli clp/pblk 0db to 18db features correlated double sampler (cds) 0 db to 18 db pixel gain amplifier ( pxga ) 6 db to 42 db 10-bit variable gain amplifier (vga) 10-bit 25 msps a/d converter black level clamp with variable level control complete on-chip timing driver precision timing core with 800 ps resolution on-chip 3 v horizontal and rg drivers 40-lead lfcsp package applications digital still cameras high speed digital imaging applications general description the ad9948 is a highly integrated ccd signal processor for digital still camera applications. specified at pixel rates of up to 25 mhz, the ad9948 consists of a complete analog front end with a/d conversion, combined with a programmable timing driver. the precision timing core allows adjustment of high speed clocks with 800 ps resolution. the analog front end includes black level clamping, cds, pxga, vga, and a 25 mhz 10-bit a/d converter. the timing driver provides the high speed ccd clock drivers for rg and h1?4. operation is programmed using a 3-wire serial interface. packaged in a space-saving 40-lead lfcsp package, the ad9948 is specified over an operating temperature range of ?0 c to +85 c.
rev. 0 ? ad9948?pecifications digital specifications parameter symbol min typ max unit logic inputs high level input voltage v ih 2.1 v low level input voltage v il 0.6 v high level input current i ih 10 a low level input current i il 10 a input capacitance c in 10 pf logic outputs high level output voltage, i oh = 2 ma v oh 2.2 v low level output voltage, i ol = 2 ma v ol 0.5 v cli input high level input voltage (tcvdd/2 + 0.5 v) v ih?li 1.85 v low level input voltage v il?li 0.85 v rg and h-driver outputs high level output voltage (rgvdd ?0.5 v and hvdd ?0.5 v) v oh 2.2 v low level output voltage v ol 0.5 v maximum output current (programmable) 30 ma maximum load capacitance 100 pf specifications subject to change without notice. general specifications parameter min typ max unit temperature range operating ?0 +85 c storage ?5 +150 c maximum clock rate 25 mhz power supply voltage avdd, tcvdd (afe, timing core) 2.7 3.0 3.6 v hvdd (h1?4 drivers) 2.7 3.0 3.6 v rgvdd (rg driver) 2.7 3.0 3.6 v drvdd (d0?9 drivers) 2.7 3.0 3.6 v dvdd (all other digital) 2.7 3.0 3.6 v power dissipation 25 mhz, hvdd = rgvdd = 3 v, 100 pf h1?4 loading * 220 mw total shutdown mode 1 mw * the total power dissipated by the hvdd supply may be approximated using the equation total hvdd power c hvdd pixel frequency hvdd number of h outputs used load = ? ()() reducing the h-loading, using only two of the outputs, and/or using a lower hvdd supply will reduce the power dissipation. specifications subject to change without notice. (t min to t max , avdd = dvdd = drvdd = hvdd = rgvdd = 2.7 v, c l = 20 pf, unless otherwise noted.)
rev. 0 ad9948 e3e analog specifications parameter min typ max unit notes cds gain 0 db allowable ccd reset transient * 500 mv max input range before saturation * 1.0 v p-p max ccd black pixel amplitude * 50 mv pixel gain amplifier (pxga) gain control resolution 256 steps gain monotonicity min gain 0 db max gain 18 db variable gain amplifier (vga) max input range 1.0 v p-p max output range 2.0 v p-p gain control resolution 1024 steps gain monotonicity guaranteed gain range min gain (vga code 0) 6 db max gain (vga code 1023) 42 db black level clamp clamp level resolution 256 steps clamp level measured at adc output min clamp level (0) 0 lsb max clamp level (255) 63.75 lsb a/d converter resolution 10 bits differential nonlinearity (dnl) e1.0 0.5 +1.0 lsb no missing codes guaranteed full-scale input voltage 2.0 v voltage reference reference top voltage (reft) 2.0 v reference bottom voltage (refb) 1.0 v system performance specifications include entire signal chain vga gain accuracy min gain (code 0) 5.0 5.5 6.0 db max gain (code 1023) 40.5 41.5 42.5 db peak nonlinearity, 500 mv input signal 0.2 % 12 db gain applied total output noise 0.25 lsb rms ac grounded input, 6 db gain applied power supply rejection (psr) 50 db measured with step change on supply * input signal characteristics defined as follows: 50mv max optical black pixel 500mv typ reset transient 1v max input signal range specifications subject to change without notice. (t min to t max , avdd = dvdd = 3.0 v, f cli = 25 mhz, typical timing specifications, unless otherwise noted.)
rev. 0 ? ad9948 timing specifications parameter symbol min typ max unit master clock (cli) (see figure 4) cli clock period t cli 40 ns cli high/low pulsewidth t adc 16 20 24 ns delay from cli to internal pixel period position t clidly 6ns clpob pulsewidth (programmable) * t cob 22 0 pixels sample clocks (see figure 6) shp rising edge to shd rising edge t s1 17 20 ns data outputs (see figures 7a and 7b) output delay from programmed edge t od 6ns pipeline delay 11 cycles serial interface maximum sck frequency f sclk 10 mhz sl to sck setup time t ls 10 ns sck to sl hold time t lh 10 ns sdata valid to sck rising edge setup t ds 10 ns sck falling edge to sdata valid hold t dh 10 ns sck falling edge to sdata valid read t dv 10 ns * minimum clpob pulsewidth is for functional operation only. wider typical pulses are recommended to achieve low noise clamp refe rence. specifications subject to change without notice. (c l = 20 pf, f cli = 25 mhz, serial timing in figure 3, unless otherwise noted.) absolute maximum ratings * with parameter respect to min max unit avdd, tcvdd avss ?.3 +3.9 v hvdd, rgvdd hvss, rgvss ?.3 +3.9 v dvdd, drvdd dvss, drvss ?.3 +3.9 v any vss any vss ?.3 +0.3 v digital outputs drvss ?.3 drvdd + 0.3 v clpob/pblk, hblk dvss ?.3 dvdd + 0.3 v sck, sl, sdata dvss ?.3 dvdd + 0.3 v rg rgvss ?.3 rgvdd + 0.3 v h1?4 hvss ?.3 hvdd + 0.3 v reft, refb, ccdin avss ?.3 avdd + 0.3 v junction temperature 150 c lead temperature (10 sec) 300 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9948 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide temperature package package model range description option ad9948kcp ?0 c to +85 c lfcsp cp-40 ad9948kcprl ?0 c to +85 c lfcsp cp-40 AD9948KCPZ * ?0 c to +85 c lfcsp cp-40 AD9948KCPZrl * ?0 c to +85 c lfcsp cp-40 * this is a lead free product. thermal characteristics thermal resistance 40-lead lfcsp package ja = 27 c/w * * ja is measured using a 4-layer pcb with the exposed paddle soldered to the board.
rev. 0 ad9948 e5e pin function descriptions pin no. mnemonic type * description 2e4 d0ed2 do data outputs (d0 is lsb) 5 drvss p digital driver ground 6 drvdd p digital driver supply 7e13 d3ed9 do data outputs (d9 is msb) 14 h1 do ccd horizontal clock 1 15 h2 do ccd horizontal clock 2 16 hvss p h1eh4 driver ground 17 hvdd p h1eh4 driver supply 18 h3 do ccd horizontal clock 3 19 h4 do ccd horizontal clock 4 20 rgvss p rg driver ground 21 rg do ccd reset gate clock 22 rgvdd p rg driver supply 23 tcvss p analog ground for timing core 24 tcvdd p analog supply for timing core 25 cli di master clock input 26 avdd p analog supply for afe 27 ccdin ai analog input for ccd signal (connect through series 0.1 f capacitor) 28 avss p analog ground for afe 29 reft ao reference top decoupling (decouple with 1.0 f to avss) 30 refb ao reference bottom decoupling (decouple with 1.0 f to avss) 31 sl di 3-wire serial load 32 sdi di 3-wire serial data input 33 sck di 3-wire serial clock 34 vd di vertical sync pulse 35 hd di horizontal sync pulse 36 dvss p digital ground 37 dvdd p digital supply 38 hblk di optional hblk input 39 clp/pblk do clpob or pblk output 1, 40 nc not internally connected * type: ai = analog input, ao = analog output, di = digital input, do = digital output, p = power. pin configuration top view ad9948 pin 1 identifier 30 refb 29 reft 28 avss 27 ccdin 26 avdd 25 cli 24 tcvdd 23 tcvss 22 rgvdd 21 rg nc 1 ( lsb) d0 2 d1 3 d2 4 drvss 5 drvdd 6 d3 7 d4 8 d5 9 d6 10 40 nc 39 clp/pblk 38 hblk 37 dvdd 36 dvss 35 hd 34 vd 33 sck 32 sdi 31 sl d7 11 d8 12 ( msb) d9 13 h1 14 h2 15 hvss 16 hvdd 17 h3 18 h4 19 rgvss 20
rev. 0 e6e ad9948 equivalent circuits r avdd avss avss circuit 1. ccdin (pin 27) avdd avss 330 enable enl nnl aa lb nl n n a lb lb lb a a n a lb 12 n lsb (adc full scale/ codes) = where n is the bit resolution of the adc. for the ad9948, 1l sb is approximately 1.95 mv. power supply rejection (psr) the psr is measured with a step change applied to the supply pins. the psr specification is calculated from the change in the data outputs for a given step change in the supply voltage.
rev. 0 t ypical performance characteristicsead9948 e7e e1.0 0 1000 400 200 600 800 e0.5 0 0.5 1.0 adc output code dnl (lsb) tpc 1. typical dnl vga gain code (lsb) 0 0 1000 400 output noise (lsb) 200 2.5 600 800 5.0 7.5 10 tpc 2. output noise vs. vga gain sample rate (mhz) 250 200 100 25 10 power dissipation (mw) 150 175 225 15 v dd = 3.3v 20 125 275 v dd = 3.0v v dd = 2.7v tpc 3. power curves
rev. 0 e8e ad9948 system overview ccd serial interface dout digital image processing asic v-driver hd, vd cli v1evx, vsg1evsgx, subck h1eh4, rg ccdin ad9948 integrated afe + td figure 1. typical application figure 1 shows the typical system application diagram for the ad9948. the ccd output is processed by the ad9948?s afe circuitry, which consists of a cds, a pxga, a vga, a black level clamp, and an a/d converter. the digitized pixel information is sent to the digital image processor chip, where all postprocessing and compression occurs. to operate the ccd, ccd timing parameters are programmed into the ad9948 from the image processor through the 3-wire serial interface. from the system master clock, cli, provided by the image processor, the ad9948 generates the high speed ccd clocks and all internal afe clocks. all ad9948 clocks are synchronized with vd and hd. all of the ad9948?s horizontal pulses (clpob, pblk, and hblk) are programmed and generated internally. the h-drivers for h1eh4 and rg are included in the ad9948, allowing these clocks to be connected directly to the ccd. h- drive voltage of 3 v is supported in the ad9948. figure 2a shows the horizontal and vertical counter dimensions for the ad9948. all internal horizontal clocking is programmed using these dimensions to specify line and pixel locations. maximum field dimensions 12-bit horizontal = 4096 pixels max 12-bit vertical = 4096 lines max figure 2a. vertical and horizontal counters vd hd max vd length is 4095 lines cli max hd length is 4095 pixels figure 2b. maximum vd/hd dimensions
rev. 0 ad9948 e9e serial interface timing all of the internal registers of the ad9948 are accessed through a 3-wire serial interface. each register consists of an 8-bit ad dress and a 24-bit data-word. both the 8-bit address and 24-bit data- word are written starting with the lsb. to write to each register, a 32-bit operation is required, as shown in figure 3a. although many registers are less than 24 bits wide, all 24 bits must be written for each register. if the register is only 16 bits wide, then the upper eight bits are don?t cares and may be filled with zeros during the serial write operation. if fewer than 24 bits are written, the register will not be updated with new data. figure 3b shows a more efficient way to write to the registers by using the ad9948?s address auto-increment capability. using this method, the lowest desired address is written first, followed by multiple 24-bit data-words. each new 24-bit data-word will be written automatically to the next highest register address. by eliminating the need to write each 8-bit address, faster register loading is achieved. address auto-increment may be used start- ing with any register location, and may be used to write to as few as two registers or as many as the entire register space. complete register listing all addresses and default values are expressed in hexadecimal. all registers are vd/hd updated as shown in figure 3a, except for the registers indicated in table i, which are sl updated. table i. sl-updated registers register description oprmode afe operation modes ctlmode afe control modes sw_reset software reset bit tgcore _rstb reset bar signal for internal tg core preventupdate prevents update of registers vdhdedge vd/hd active edge fieldval resets internal field pulse hblkretime retimes the hblk to internal clock clpblkout clp/blk output pin select clpblken enables clp/blk output pin h1control h1/h2 polarity control rgcontrol h1 positive edge location drvcontrol h1 negative edge location sampcontrol h1 drive current doutphase h2 drive current sdata a0 a1 a2 a4 a5 a6 a7 d0 d1 d2 d3 d21 d22 d23 sck sl a3 notes 1. individual sdata bits are latched on sck rising edges. 2. all 32 bits must be written: 8 bits for address and 24 bits for data. 3. if the register length is <24 bits, then don?t care bits must be used to complete the 24-bit data length. 4. new data is updated at either the sl rising edge or at the hd falling edge after the next vd falling edge. 5. vd/hd update position may be delayed to any hd falling edge in the field using the update register. t dh t ls t lh t ds vd sl updated vd/hd updated hd ... ... ... ... ... 8-bit address 24-bit data 1 32 2345678910 11 12 30 31 figure 3a. serial write operation sdata a0 a1 a2 a4 a5 a6 a7 d0 d1 d22 d23 sck sl a3 notes 1. multiple sequential registers may be loaded continuously. 2. the first (lowest address) register address is written, followed by multiple 24-bit data-words. 3. the address will automatically increment with each 24-bit data-word (all 24 bits must be written). 4. sl is held low until the last desired register has been loaded. 5. new data is updated at either the sl rising edge or at the hd falling edge after the next vd falling edge. d0 d1 d22 d23 d0 ... ... ... data for starting register address data for next register address d2 d1 ... ... ... ... ... ... 1 32 2345678910 31 34 33 56 55 58 57 59 figure 3b. continuous serial write operation
rev. 0 e10e ad9948 table ii. afe register map data bit default address content value name description 00 [11:0] 4 oprmode afe operation modes. (see table viii.) 01 [9:0] 0 vgagain vga gain. 02 [7:0] 80 clamp level optical black clamp level. 03 [11:0] 4 ctlmode afe control modes. (see table ix.) 04 [17:0] 0 pxga gain01 pxga gain registers for color 0 [8:0] and color 1 [17:9]. 05 [17:0] 0 pxga gain23 pxga gain registers for color 2 [8:0] and color 3 [17:9]. table iii. miscellaneous register map data bit default address content value name description 10 [0] 0 sw_rst software reset. 1 = reset all registers to default, then self-clear back to 0. 11 [0] 0 out_control output control. 0 = make all dc outputs inactive. 12 [0] 0 tgcore_rstb timing core reset bar. 0 = reset tg core. 1 = resume operation. 13 [11:0] 0 update serial update. sets the line (hd) within the field to update serial data. 14 [0] 0 preventupdate prevents the update of the vd-updated registers. 1 = prevent update. 15 [0] 0 vdhdedge vd/hd active edge. 0 = falling edge triggered. 1 = rising edge triggered. 16 [1:0] 0 fieldval field value sync. 0 = next field 0. 1 = next field 1. 2/3 = next field 2. 17 [0] 0 hblkretime retime hblk to internal h1 clock. preferred setting is 1. setting to 1 will add one cycle delay to hblk toggle positions. 18 [1:0] 0 clpblkout clp/blk pin output select. 0 = clpob. 1 = pblk. 2 = hblk. 3 = low. 19 [0] 1 clpblken enable clp/blk output. 1 = enable. 1a [0] 0 test mode internal test mode. should always be set low.
rev. 0 ad9948 e11e table iv. clpob register map data bit default address content value (hex) name description 20 [3:0] f clpobpol start polarities for clpob sequences 0, 1, 2, and 3. 21 [23:0] ffffff clpobtog_0 sequence 0. toggle position 1 [11:0] and toggle position 2 [23:12]. 22 [23:0] ffffff clpobtog_1 sequence 1. toggle position 1 [11:0] and toggle position 2 [23:12]. 23 [23:0] ffffff clpobtog_2 sequence 2. toggle position 1 [11:0] and toggle position 2 [23:12]. 24 [23:0] ffffff clpobtog_3 sequence 3. toggle position 1 [11:0] and toggle position 2 [23:12]. 0 clpobscp0 clpob sequence-change-position 0 (hard-coded to 0). 25 [7:0] 0 clpobsptr clpob sequence pointers for region 0 [1:0], 1 [3:2], 2 [5:4], 3 [7:6]. 26 [11:0] fff clpobscp1 clpob sequence-change-position 1. 27 [11:0] fff clpobscp2 clpob sequence-change-position 2. 28 [11:0] fff clpobscp3 clpob sequence-change-position 3. table v. pblk register map data bit default address content value (hex) name description 30 [3:0] f pblkpol start polarities for pblk sequences 0, 1, 2, and 3. 31 [23:0] ffffff pblktog_0 sequence 0. toggle position 1 [11:0] and toggle position 2 [23:12]. 32 [23:0] ffffff pblktog_1 sequence 1. toggle position 1 [11:0] and toggle position 2 [23:12]. 33 [23:0] ffffff pblktog_2 sequence 2. toggle position 1 [11:0] and toggle position 2 [23:12]. 34 [23:0] ffffff pblktog_3 sequence 3. toggle position 1 [11:0] and toggle position 2 [23:12]. 0 pblkscp0 pblk sequence-change-position 0 (hard-coded to 0). 35 [7:0] 0 pblksptr pblk sequence pointers for region 0 [1:0], 1 [3:2], 2 [5:4], 3 [7:6]. 36 [11:0] fff pblkscp1 pblk sequence-change-position 1. 37 [11:0] fff pblkscp2 pblk sequence-change-position 2. 38 [11:0] fff pblkscp3 pblk sequence-change-position 3.
rev. 0 ?2 ad9948 table vi. hblk register map data bit default address content value (hex) name description 40 [0] 0 hblkdir hblk internal/external. 0 = internal. 1 = external. 41 [0] 0 hblkpol hblk external active polarity. 0 = active low. 1 = active high. 42 [0] 1 hblkextmask hblk external masking polarity. 0 = mask h1 low. 1 = mask h1high. 43 [3:0] f hblkmask hblk internal masking polarity. 0 = mask h1 low. 1 = mask h1 high. 44 [23:0] ffffff hblktog12_0 sequence 0. toggle position 1 [11:0] and toggle position 2 [23:12]. 45 [23:0] ffffff hblktog34_0 sequence 0. toggle position 3 [11:0] and toggle position 4 [23:12]. 46 [23:0] ffffff hblktog56_0 sequence 0. toggle position 5 [11:0] and toggle position 6 [23:12]. 47 [23:0] ffffff hblktog12_1 sequence 1. toggle position 1 [11:0] and toggle position 2 [23:12]. 48 [23:0] ffffff hblktog34_1 sequence 1. toggle position 3 [11:0] and toggle position 4 [23:12]. 49 [23:0] ffffff hblktog56_1 sequence 1. toggle position 5 [11:0] and toggle position 6 [23:12]. 4a [23:0] ffffff hblktog12_2 sequence 2. toggle position 1 [11:0] and toggle position 2 [23:12]. 4b [23:0] ffffff hblktog34_2 sequence 2. toggle position 3 [11:0] and toggle position 4 [23:12]. 4c [23:0] ffffff hblktog56_2 sequence 2. toggle position 5 [11:0] and toggle position 6 [23:12]. 4d [23:0] ffffff hblktog12_3 sequence 3. toggle position 1 [11:0] and toggle position 2 [23:12]. 4e [23:0] ffffff hblktog34_3 sequence 3. toggle position 3 [11:0] and toggle position 4 [23:12]. 4f [23:0] ffffff hblktog56_3 sequence 3. toggle position 5 [11:0] and toggle position 6 [23:12]. 0 hblkscp0 hblk sequence-change-position 0 (hard-coded to 0). 50 [7:0] 0 hblksptr hblk sequence pointers for region 0 [1:0], 1 [3:2], 2 [5:4], 3 [7:6]. 51 [11:0] fff hblkscp1 hblk sequence-change-position 1. 52 [11:0] fff hblkscp2 hblk sequence-change-position 2. 53 [11:0] fff hblkscp3 hblk sequence-change-position 3. table vii. h1?2, rg, shp, shd register map data bit default address content value name description 60 [12:0] 01001 h1control h1 signal control. polarity [0] (0 = inversion, 1 = no inversion). h1 positive edge location [6:1]. h1 negative edge location [12:7]. 61 [12:0] 00801 rgcontrol rg signal control. polarity [0] (0 = inversion, 1 = no inversion). rg positive edge location [6:1]. rg negative edge location [12:7]. 62 [14:0] 0 drvcontrol drive strength control for h1 [2:0], h2 [5:3], h3 [8:6], h4 [11:9], and rg [14:12]. drive current values: 0 = off, 1 = 4.3 ma, 2 = 8.6 ma, 3 = 12.9 ma, 4 = 17.2 ma, 5 = 21.5 ma, 6 = 25.8 ma, 7 = 30.1 ma. 63 [11:0] 00024 sampcontrol shp/shd sample control. shp sampling location [5:0]. shd sampling location [11:6]. 64 [5:0] 0 doutphase dout phase control.
rev. 0 ad9948 e13e table viii. afe operation register detail data bit default address content value name description 00 [1:0] 0 pwrdown 0 = normal operation. 1 = reference standby. 2/3 = total power-down. [2] 1 clpenable 0 = disable ob clamp. 1 = enable ob clamp. [3] 0 clpspeed 0 = select normal ob clamp settling. 1 = select fast ob clamp settling. [4] 0 fastupdate 0 = ignore vga update. 1 = very fast clamping when vga is updated. [5] 0 pblk_lvl dout value during pblk. 0 = blank to zero. 1 = blank to clamp level. [7:6] 0 test mode test operation only. set to zero. [8] 0 dcbyp 0 = enable dc restore circuit. 1 = bypass dc restore circuit during pblk. [9] 0 testmode test operation only. set to zero. [11:10] 0 cdsgain adjustment of cds gain. 0 = 0 db. 01= e2 db. 10 = e4 db. 11 = 0 db. table ix. afe control register detail data bit default address content value name description 04 [1:0] 0 colorsteer 0 = off. 1 = progressive. 2 = interlaced. 3 = three field. [2] 1 pxgaenable 0 = disable pxga. 1 = enable pxga. [3] 0 doutdisable 0 = data outputs are driven. 1 = data outputs are three-stated. [4] 0 doutlatch 0 = latch data outputs with dout phase. 1 = output latch transparent. [5] 0 grayencode 0 = binary encode data outputs. 1= gray encode data outputs.
rev. 0 e14e ad9948 precision timing high speed timing generation the ad9948 generates flexible high speed timing signals using the precision timing core. this core is the foundation for gener- ating the timing used for both the ccd and the afe; the reset gate rg, horizontal drivers h1eh4, and the shp/shd sample clocks. a unique architecture makes it routine for the system designer to optimize image quality by providing precise control over the horizontal ccd readout and the afe correlated double sampling. timing resolution the precision timing core uses a 1 master clock input (cli) as a reference. this clock should be the same as the ccd pixel clock frequency. figure 4 illustrates how the internal timing core divides the master clock period into 48 steps or edge positions. therefore, the edge resolution of the precision timing core is (t cli /48). for more information on using the cli input, refer to the applications information section. high speed clock programmability figure 5 shows how the high speed clocks, rg, h1eh4, shp, and shd, are generated. the rg pulse has programmable rising and falling edges, and may be inverted using the polarity control. the horizontal clocks h1 and h3 have programmable rising and falling edges, and polarity control. the h2 and h4 clocks are always inverses of h1 and h3, respectively. table x summarizes the high speed timing registers and their parameters. each edge location setting is 6 bits wide, but only 48 valid edge locations are available. therefore, the register values are mapped into four quadrants, with each quadrant containing 12 edge locations. table xi shows the correct register values for the corresponding edge locations. notes 1. pixel clock period is divided into 48 positions, providing fine edge resolution for high speed clocks. 2. there is a fixed delay from the cli input to the internal pixel period positions ( t clidly = 6 ns typ). p[0] p[48] = p[0] p[12] p[24] p[36] 1 pixel period ... ... cli t clidly position figure 4. high speed clock resolution from cli master clock input h1/h3 h2/h4 ccd signal rg (1) (2) (3) (4) (5) (6) programmable clock positions: 1. rg rising edge 2. rg falling edge 3. shp sample location 4. shd sample location 5. h1/h3 rising edge position 6. h1/h3 falling edge position (h2/h4 are inverse of h1/h3) figure 5. high speed clock programmable locations table x. h1control, rgcontrol, drvcontrol, and sampcontrol register parameters parameter length range description polarity 1b high/low polarity control for h1/h3 and rg (0 = no inversion, 1 = inversion). positive edge 6b 0e47 edge location positive edge location for h1/h3 and rg. negative edge 6b 0e47 edge location negative edge location for h1/h3 and rg. sample location 6b 0e47 sample location sampling location for shp and shd. drive control 3b 0e7 current steps drive current for h1eh4 and rg outputs, 0e7 steps of 4.1 ma each. dout phase 6b 0e47 edge location phase location of data outputs with respect to pixel period.
rev. 0 ad9948 e15e table xi. precision timing edge locations quadrant edge location (decimal) register value (decimal) register value (binary) i0 to 11 0 to 11 000000 to 001011 ii 12 to 23 16 to 27 010000 to 011011 iii 24 to 35 32 to 43 100000 to 101011 iv 36 to 47 48 to 59 110000 to 111011 h-driver and rg outputs in addition to the programmable timing positions, the ad9948 features on-chip output drivers for the rg and h1eh4 outputs. these drivers are powerful enough to directly drive the ccd inputs. the h-driver and rg driver current can be adjusted for optimum rise/fall time into a particular load by using the drvcontrol register (address x062). the drvcontrol register is divided into five different 3-bit values, each one being adjustable in 4.1 ma increments. the minimum setting of 0 is equal to off or three-state, and the maximum setting of 7 is equal to 30.1 ma. as shown in figure 6, the h2/h4 outputs are inverses of h1/h3. the internal propagation delay resulting from the signal inversion is less than l ns, which is significantly less than the typical rise time driving the ccd load. this results in a h1/h2 crossover voltage at approximately 50% of the output swing. the crossover voltage is not programmable. digital data outputs the ad9948 data output phase is programmable using the doutphase register (address x064). any edge from 0 to 47 may be programmed, as shown in figure 7a. the pipeline delay for the digital data output is shown in figure 7b. fixed crossover voltage h1/h3 h2/h4 t pd h2/h4 h1/h3 t rise t pd t rise << figure 6. h-clock inverse phase relationship notes 1. digital output data (dout) phase is adjustable with respect to the pixel period. 2. within one clock period, the data transition can be programmed to any of the 48 locations. p[0] p[48] = p[0] cli 1 pixel period p[12] p[24] p[36] dout t od figure 7a. digital output phase adjustment notes default timing values are shown: shdloc = 0, dout phase = 0. higher values of shd and/or doutphase will shift dout transition to the right, with respect to cli location. dout ccdin cli shd (internal) n n+1 n+2 n+12 n+11 n+10 n+9 n+8 n+7 n+6 n+5 n+4 n+3 n+13 ne13 ne3 ne4 ne5 ne6 ne7 ne8 ne9 ne10 ne11 ne12 ne2 ne1 n+1 n sample pixel n pipeline latency = 11 cycles t clidly ne1 figure 7b. pipeline delay for digital data output
rev. 0 e16e ad9948 horizontal clamping and blanking the ad9948?s horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. individual sequences are defined for each signal, which are then organized into multiple regions during image readout. this allows the dark pixel clamping and blanking patterns to be changed at each stage of the readout to accommodate different image transfer timing and high speed line shifts. individual clpob and pblk sequences the afe horizontal timing consists of clpob and pblk, as shown in figure 8. these two signals are independently pro- grammed using the parameters shown in table xii. the start polarity, first toggle position, and second toggle position are fully programmable for each signal. the clpob and pblk signals are active low, and should be programmed accordingly. up to four individual sequences can be created for each signal. individual hblk sequences the hblk programmable timing shown in figure 9 is similar to clpob and pblk. however, there is no start polarity con- trol. only the toggle positions are used to designate the start and the stop positions of the blanking period. additionally, there is a polarity control, hblkmask, which designates the polarity of the horizontal clock signals h1eh4 during the blanking period. setting hblkmask high will set h1 = h3 = low and h2 = h4 = high during the blanking, as shown in figure 10. up to four individual sequences are available for hblk. (3) (2) (1) hd clpob pblk . . . programmable settings: 1. start polarity (clamp and blank region are active low) 2. first toggle position 3. second toggle position . . . active active figure 8. clamp and preblank pulse placement (2) (1) hd hblk . . . programmable settings: 1. first toggle position = start of blanking 2. second toggle position = end of blanking . . . blank blank figure 9. horizontal blanking (hblk) pulse placement table xii. clpob and pblk individual sequence parameters parameter length range description polarity 1b high/low starting polarity of clamp and pblk pulses for sequences 0e3. toggle position 1 12b 0e4095 pixel location first toggle position within the line for sequences 0e3. toggle position 2 12b 0e4095 pixel location second toggle position within the line for sequences 0e3. table xiii. hblk individual sequence parameters parameter length range description hblkmask 1b high/low m asking polarity for h1 for sequences 0e3 (0 = h1 low, 1 = h1 high). toggle position 1 12b 0e4095 pixel location first toggle position within the line for sequences 0e3. toggle position 2 12b 0e4095 pixel location second toggle position within the line for sequences 0e3. toggle position 3 12b 0e4095 pixel location third toggle position within the line for sequences 0e3. toggle position 4 12b 0e4095 pixel location fourth toggle position within the line for sequences 0e3. toggle position 5 12b 0e4095 pixel location fifth toggle position within the line for sequences 0e3. toggle position 6 12b 0e4095 pixel location sixth toggle position within the line for sequences 0e3.
rev. 0 ad9948 e17e hd hblk . . . the polarity of h1 during blanking is programmable (h2 is opposite polarity of h1). . . . h1/h3 h1/h3 h2/h4 . . . . . . figure 10. hblk masking control hblk special h-blank pattern is created using multiple hblk toggle positions. h1/h3 h2/h4 tog1 tog2 tog3 tog4 tog5 tog6 figure 11. generating special hblk patterns generating special hblk patterns six toggle positions are available for hblk. normally, only t wo of the toggle positions are used to generate the standard hblk interval. however, the additional toggle positions may be used to generate special hblk patterns, as shown in figure 11. the pattern in this example uses all six toggle positions to generate two extra groups of pulses during the hblk inter- val. by changing the toggle positions, different patterns can be created. horizontal sequence control the ad9948 uses sequence change positions (scps) and sequence pointers (sptrs) to organize the individual horizontal sequences. up to four scps are available to divide the readout into four separate regions, as shown in figure 12. the scp 0 is always hard- coded to line 0, and scp1escp3 are register programmable. d uring each region bounded by the sc p, the sptr registers designate which sequence is used by each signal. clpob, pblk, and hblk each have a separate set of scps. for example, clpobscp1 will define region 0 for clpob, and in that region, any of the four individual clpob sequences may be selected with the clpobsptr register. the next scp defines a new region, and in that region each signal can be assigned to a different individual sequence. the sequence control registers are sum- ma rized in table xiv. external hblk signal the ad9948 can also be used with an external hblk signal. set- ting the hblkdir register (address x040) to high will disable the internal hblk signal generation. the polarity of the external signal is specified using the hblkpol register, and the mask- ing polarity of h1 is specified using the hblkmask register. table xv summarizes the register values when using an external hblk signal. table xiv. horizontal sequence control parameters for clpob, pblk, and hblk register length range description scp 12b 0e4095 line number clob/pblk/hblk scp to define horizontal regions 0e3. sptr 2b 0e3 sequence number sequence pointer for horizontal regions 0e3.
rev. 0 e18e ad9948 up to four individual horizontal clamp and blanking regions may be programmed within a single field, using the sequence change positions. sequence change of position 1 sequence change of position 2 sequence change of position 3 single field (1 vd interval) clamp and pblk sequence region 0 sequence change of position 0 (v-counter = 0) clamp and pblk sequence region 3 clamp and pblk sequence region 2 clamp and pblk sequence region 1 figure 12. clamp and blanking sequence flexibility table xv. external hblk register parameters register length range description hblkdir 1b high/low specifies hblk internally generated or externally supplied. 1 = external. hblkpol 1b high/low external hblk active polarity. 0 = active low. 1 = active high. hblkextmask 1b high/low external hblk masking polarity. 0 = mask h1 low. 1 = mask h1 high. 000 1 12 111 0 03 11 00 012345678910111214150123 023 h-counter reset vd notes 1. internal h-counter is reset seven cli cycles after the hd falling edge (when using vdhdedge = 0). 2. typical timing relationship: cli rising edge coincides with hd falling edge. 3. pxga steering is synchronized with the reset of the internal h-counter (mosaic separate mode is shown). hd xx xxx x x pxga gain register cli xx xxx x x h-counter (p ixel counter) x x x x x x figure 13. h-counter synchronization h-counter synchronization the h-counter reset occurs seven cli cycles following the hd falling edge. the pxga steering is synchronized with the reset of the internal h-counter (see figure 13).
rev. 0 ad9948 e19e power-up procedure vdd (input) serial writes vd (output) 1 h odd field even field ... ... digital outputs clocks active when out_control register is updated at vd/hd edge h1/h3, rg h2/h4 t pwr cli (input) hd (output) 1v ... ... figure 14. recommended power-up sequence recommended power-up sequence when the ad9948 is powered up, the following sequence is recommended (refer to figure 14 for each step): 1. turn on the power supplies for the ad9948. 2. apply the master clock input, cli, vd, and hd. 3. although the ad9948 contains an on-chip power-on reset, a software reset of the internal registers is recommended. write a 1 to the sw_rst register (address x010), which will reset all the internal registers to their default values. this bit is self-clearing and will automatically be reset back to 0. 4. the precision timing core must be reset by writing a 0 to the tgcore_rstb register (address x012) followed by writing a l to the tgcore_rstb register. this will start the internal timing core operation. 5. write a 1 to the preventupdate register (address x014). this will prevent the updating of the serial register data. 6. write to the desired registers to configure high speed timing and horizontal timing. 7. write a 1 to the out_control register (address x011). this will allow the outputs to become active after the next vd/hd rising edge. 8. write a 0 to the preventupdate register (address x014). this will allow the serial information to be updated at next vd/hd falling edge. the next vd/hd falling edge allows register updates to occur, including out_control, which enables all clock outputs.
rev. 0 e20e ad9948 6db ~ 42db ccdin digital filter clpob dc restore optical black clamp 10-bit adc vga dac clamp level register 8 vg a gain register cds internal v ref 2v full scale 0db ~ 18db 10 precision timing generation shp shd pxga 1.5v output data latch reft refb dout phase v- h timing generation shp shd dout phase clpob pblk pblk 1.0v 2.0v dout ad9948 pxga gain registers 0db, e2db, e4db 1.0
rev. 0 ad9948 e21e line0 gain0, gain1, gain0, gain1, ... rr gr gr line1 line2 gain2, gain3, gain2, gain3, ... gain0, gain1, gain0, gain1, ... color steering mode: progressive rr gr gr gb b ccd: progressive bayer gb b gb b gb b figure 17a. ccd color filter example?progressive scan the same bayer pattern can also be interlaced, and the interlaced mode should be used with this type of ccd (see figure 17b). the color steering performs the proper multiplexing of the r, g, and b gain values (loaded into the pxga gain registers), and is synchronized by the user with vertical (vd) and horizontal (hd) sync pulses. for timing information, see figure 18b. line0 gain0, gain1, gain0, gain1, ... rr gr gr line1 line2 gain0, gain1, gain0, gain1, ... gain0, gain1, gain0, gain1, ... gb gb bb line0 gain2, gain3, gain2, gain3, ... line1 line2 gain2, gain3, gain2, gain3, ... gain2, gain3, gain2, gain3, ... color steering mode: interlaced gb gb bb gb gb bb gb gb bb rr gr gr rr gr gr rr gr gr even field odd field ccd: interlaced bayer figure 17b. ccd color filter example?interlaced readout a third type of readout uses the bayer pattern divided into three different readout fields. the three-field mode should be used with this type of ccd (see figure 17c). the color steering performs the proper multiplexing of the r, g, and b gain values (loaded into the pxga gain registers), and is synchronized by the user with vertical (vd) and horizontal (hd) sync pulses. for timing information, see figure 18c. line0 gain0, gain1, gain0, gain1, ... rr gr gr line1 line2 gain2, gain3, gain2, gain3, ... gain0, gain1, gain0, gain1, ... line0 gain2, gain3, gain2, gain3, ... line1 line2 gain0, gain1, gain0, gain1, ... gain2, gain3, gain2, gain3, ... color steering mode: three field gb gb bb gb gb bb rr gr gr first field second field ccd: 3-field readout line0 gain0, gain1, gain0, gain1, ... rr gr gr line1 line2 gain2, gain3, gain2, gain3, ... gain0, gain1, gain0, gain1, ... rr gr gr third field gb gb bb gb gb bb rr gr gr rr gr gr gb gb bb gb gb bb figure 17c. ccd color filter example?three-field readout
rev. 0 e22e ad9948 220 33 1 1 vd notes 1. vd falling edge will reset the pxga gain register steering to 0101 line. 2. hd falling edges will alternate the pxga gain register steering between 0101 and 2323 lines. 3. fieldval is always reset to 0 on vd falling edges. hd 11 0 x x pxga gain register fieldval 0 fieldval = 0 0220 33 1 1 11 0 0 0 0 fieldval = 0 figure 18a. pxga color steering?progressive mode 00 3 11 2 2 vd notes 1. fieldval = 0 (start of first field) will reset the pxga gain register steering to 0101 line. 2. fieldval = 1 (start of second field) will reset the pxga gain register steering to 2323 line. 3. hd falling edges will reset the pxga gain register steering to either 0 (fieldval = 0) or 2 (fieldval = 1). 4. fieldval will toggle between 0 and 1 on each vd falling edge. hd 11 0 x x pxga gain register fieldval 0 fieldval = 0 311 00 0 0 33 2 2 1 1 fieldval = 1 fieldval = 0 figure 18b. pxga color steering?interlaced mode 22 3 33 2 2 vd notes 1. fieldval = 0 (start of first field) will reset the pxga gain register steering to 0101 line. 2. fieldval = 1 (start of second field) will reset the pxga gain register steering to 2323 line. 2. fieldval = 2 (start of third field) will reset the pxga gain register steering to 0101 line. 3. hd falling edges will alternate the pxga gain register steering between 0101 and 2323 lines. 4. fieldval will increment at each vd falling edge, repeating the 0...1...2...0...1...2 pattern. hd 11 0 x x pxga gain register fieldval 0 fieldval = 0 311 00 2 2 00 1 1 3 3 fieldval = 1 fieldval = 2 figure 18c. pxga color steering?three-field mode
rev. 0 ad9948 e23e the pxga gain for each of the four channels is variable from 0 db to 18 db in 512 steps, specified using the pxga gain01 and pxga gain23 registers. the pxga gain curve is shown in figure 19. the pxga gain01 registers contains nine bits each for pxga gain0 and gain1, and the pxga gain23 registers contains nine bits each for pxga gain2 and gain3. pxga gain register code 18 0 pxga gain (db) 64 128 192 256 320 384 448 511 15 12 9 6 3 0 figure 19. pxga gain curve variable gain amplifier the vga stage provides a gain range of 6 db to 42 db, program- mable w ith 10-bit resolution through the serial digital interface. the minimum gain of 6 db is needed to match a 1 v input signal with the adc full-scale range of 2 v. when compared to 1 v full-scale systems, the equivalent gain range is 0 db to 36 db. the vga gain curve follows a linear-in-db characteristic. the exact vga gain can be calculated for any gain register value by using the equation gain db code db ()(. ) =+ 0 0351 6 where the code range is 0 to 1023. there is a restriction on the maximum amount of gain that can be applied to the signal. the pxga can add as much as 18 db, and the vga is capable of providing up to 42 db. however, the maximum total gain from the pxga and vga is restricted to 42 db. if the registers are programmed to specify a total gain higher than 42 db, the total gain will be clipped at 42 db. vga gain register code 42 0 vga gain (db) 127 255 383 511 639 767 895 1023 36 30 24 18 12 6 figure 20. vga gain curve (pxga not included) a/d converter the ad9948 uses a high performance adc architecture, opti- mized for high speed and low power. differential nonlinearity (dnl) performance is typically better than 0.5 lsb. the adc uses a 2 v input range. see tpc 1 and tpc 2 for typical linearity and noise performance plots for the ad9948. optical black clamp the optical black clamp loop is used to remove residual offsets in the signal chain and to track low frequency variations in the ccd?s black level. during the optical black (shielded) pixel interval on each line, the adc output is compared with a fixed black level reference, selected by the user in the clamp level register. the value can be progr ammed between 0 lsb and 63.75 lsb in 256 steps. the resulting error signal is filtered to reduce noise, and the correction value is applied to the adc input through a d/a converter. normally, the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. if external digital clamping is used during the postprocessing, the ad9948 optical black clamping may be disabled using bit d2 in the oprmode register. when the loop is disabled, the clamp level register may still be used to provide programmable offset adjustment. the clpob pulse should be placed during the ccd?s optical black pixels. it is recommended that the clpob pulse duration be at least 20 pixels wide to minimize clamp noise. shorter pulsewidths may be used, but clamp noise may increase and the ability to track low frequency variations in the black level will be reduced. see the horizontal clamping and blanking and the applications information sections for timing examples. digital data outputs the ad9948 digital output data is latched using the dout phase register value, as shown in figure 15. output data timing is shown in figure 7. it is also possible to leave the output latches transparent, so that the data outputs are valid immediately from the a/d converter. programming the afe control register bit d4 to a 1 will set the output latches transparent. the data outputs can also be disabled (three-stated) by setting the afe control register bit d3 to a 1. the data output coding is normally straight binary, but the coding my be changed to gray coding by setting the afe control r egister bit d5 to a 1.
rev. 0 e24e ad9948 3v analog supply serial interface 3 ccd signal vd/hd/hblk inputs clp/blk output 4 3v driver supply rg driver supply h driver supply master clock input 3v analog supply data outputs 10 h1eh4 4 top view ad9948 pin 1 identifier 30 refb 29 reft 28 avss 27 ccdin 26 avdd 25 cli 24 tcvdd 23 tcvss 22 rgvdd 21 rg nc 1 d1 3 d2 4 drvdd 6 d3 7 d4 8 d5 9 d6 10 40 nc 39 clp/pblk 38 hblk 37 dvdd 36 dvss 35 hd 34 vd 33 sck 32 sdi 31 sl d7 11 d8 12 (msb) d9 13 h1 14 h2 15 hvss 16 hvdd 17 h3 18 h4 19 rgvss 20 rg output + + + + drvss 5 ( lsb) d0 2 4.7
rev. 0 ad9948 e25e driving the cli input the ad9948?s master clock input (cli) may be used in two different configurations, depending on the application. figure 23a shows a typical dc-coupled input from the master clock source. when the dc-coupled technique is used, the master clock si gnal should be at standard 3 v cmos logic levels. as shown in figure 23b, a 1000 pf ac coupling capacitor may be used between the clock source and the cli input. in this configura- tion, the cli input will self-bias to the proper dc voltage level of approximately 1.4 v. when the ac-coupled technique is used, the master clock signal can be as low as 500 mv in amplitude. 18 ccd imager signal out 19 14 15 21 27 h2 rg h3 h4 h1 h2 h1 rg ad9948 ccdin figure 22a. ccd connections (2 h-clock) ccd imager signal out 14 15 21 27 rg h3 h4 h2 h1 rg ad9948 ccdin h2 h1 18 19 h1 h2 figure 22b. ccd connections (4 h-clock) cli 25 master clock ad9948 asic figure 23a. cli connection, dc-coupled cli 25 master clock ad9948 asic lpf 1nf figure 23b. cli connection, ac-coupled
rev. 0 e26e ad9948 horizontal timing sequence example figure 24 shows an example ccd layout. the horizontal regis- ter contains 28 dummy pixels, which will occur on each line clocked from the ccd. in the vertical direction, there are 10 optical black (ob) lines at the front of the readout and two at the back of the readout. the horizontal direction has four ob pixels in the front and 48 in the back. to configure the ad9948 horizontal signals for this ccd, three sequences can be used. figure 25 shows the first sequence, to be used during vertical blanking. during this time, there are no valid ob pixels from the sensor, so the clpob signal is not used. pblk may be enabled during this time, because no valid data is available. figure 26 shows the recommended sequence for the vertical ob interval. the clamp signals are used across the whole lines in order to stabilize the clamp loop of the ad9948. figure 27 shows the recommended sequence for the effective pixel readout. the 48 ob pixels at the end of each line are used for the clpob signal. v h us e sequence 2 us e sequence 3 se quence 2 (optional) h orizontal ccd register e ffective image area 28 dummy pixels 48 ob pixels 4 ob pixels 10 vertical ob lines 2 vertical ob lines figure 24. example ccd configuration vertical shift vert shift se quence 1: vertical blanking ccdin shp shd h1/h3 h2/h4 hblk pblk clpob dummy invalid pixels invalid pix figure 25. horizontal sequence during vertical blanking
rev. 0 ad9948 e27e vertical shift vert shift se quence 2: vertical optical black lines ccdin shp shd h1/h3 h2/h4 hblk pblk clpob optical black dummy optical black figure 26. horizontal sequences during vertical optical black pixels vertical shift vert shift se quence 3: effective pixel lines ccdin shp shd h1/h3 h2/h4 hblk pblk clpob optical black dummy effective pixels ob optical black figure 27. horizontal sequences during effective pixels
rev. 0 c03752e0e5/03(0) e28e ad9948 outline dimensions 40-lead lead frame chip scale package [lfcsp] 6 mm

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